The present invention relates to electrical circuit boards, and in particular to improved multilayer circuit board constructions and methods.
Multilayer "printed" circuit boards are widely used, and a number of different methods for making them are known in the art. Standard industry practice is to laminate a number of single layer circuit boards together, after which their metallic conductor patterns are selectively interconnected. Typically, the constituent single layer boards are bonded together using intermediate layers of an adhesive material and the application of heat and pressure. Then, after holes are drilled through the laminated structure at predetermined points, the hole walls are metal plated to interconnect the various circuit patterns electrically.
Other known multilayer circuit board fabrication processes include those shown and described in U.S. Pat. Nos. 3,464,855; 3,691,632; 3,791,858; 3,934,355 and 4,030,190.
In U.S. Pat. No. 3,464,855 to Shaheen et al., solid metal interconnections are formed between the different circuit patterns in a multilayer structure. The process described involves adhering a removable insulating mask to a circuit board overlying a conductor pattern of the board. Openings in the mask define the locations of desired interconnections between that pattern and another one to be provided subsequently. The mask openings are filled with metal, after which the removable mask is replaced with a permanent insulating layer. Only the top surfaces of the metal interconnecting members remain exposed for connection to the metal pattern subsequently formed on the insulating layer. The process is repeated as desired to form additional layers.
U.S. Pat. No. 3,691,632 to Smith concerns a variation of the perviously-mentioned industry standard method. The metal conductor patterns on an undrilled double-sided circuit board are covered with continuous layers of an insulating material. Additional metal conductor patterns are then formed on the insulating layers, and the insulation/metal pattern sequence is repeated as necessary to provide the total number of layers desired. Holes are drilled through the assembly at selected locations, intersecting the metal conductor patterns, after which metal is plated in the hole bores to interconnect the patterns electrically.
In U.S. Pat. No. 3,791,858 to McPherson et al., a multilayer process using additive techniques for forming the conductors within and between each circuit pattern layer is disclosed. The conductors are built up by metal deposition through photosensitive masks that are removed subsequently and replaced with fluid dielectric curable to solid form. Multiple layers are formed by successively repeating the process.
Another additive multilayer fabrication process is disclosed in U.S. Pat. No. 3,934,355 to Nelson. A suitable substrate is coated with a photo-polymerizable material that is exposed to light to form a dielectric layer on the substrate. A conductor pattern is formed on the dielectric layer by first image-wise exposing a photosensitve sensitizing coating applied to the layer, then electrolessly plating metal on the exposed areas. Additional layers are formed in a similar manner, windows being provided in subsequent dielectric layers for interconnection of the different conductor patterns.
U.S. Pat. No. 4,030,190 to Varker describes the construction of multilayer circuit boards by a method that begins with the lamination of dielectric material to the opposite sides of a metal base sheet. Metal conductor patterns are formed on the dielectric layers, after which additional layers of dielectric material are laminated onto the patterns. Vias for interconnection of the conductor patterns with ones subsequently formed are opened in the latter-mentioned dielectric layers by laser drilling.
Several disadvantages attend these and other prior art multilayer circuit board methods and constructions. For example, as board size and complexity increase it becomes more and more difficult to maintain good registration between the various layers in a laminated structure. The subsequently drilled and metal plated interconnection holes may not intercept the overlaid circuit patterns properly if the different layers are misregistered. Depending on the degree of misalignment, electrical short circuits, opens, and high resistance interconnections can result. Smearing of the laminate dielectric during the hole drilling process can partially or completely cover the edges of the metal conductor patterns, forming insulating barriers between the patterns and the subsequently deposited through-hole plating.
A further significant disadvantage of standard multilayer processes is the small area of the electrical connections formed between the circuit patterns and hole plating, even when the previously mentioned problems are avoided. At best, each pattern is joined to the through-hole plating by a narrow annulus of metal the same thickness as the pattern. Because of this, process irregularities can very significantly affect board reliability and yield. The problem of small area interconnections has been addressed previously by the provision of solid metal post-like connections between layers, as exemplified by the earlier mentioned patents to Shaheen et al., McPherson et al. and Varker. While satisfactory for certain uses, processes that produce only solid interlayer connections are unsuitable for most multilayer board applications, which utilize throughholes for attaching wire leads, mounting components etc. Since such holes must be provided in any event, it is a significant advantage to be able to connect different circuit patterns electrically at the through-holes. It is accordingly evident that a need exists for an improved multilayer circuit board fabrication method providing large area through-hole interlayer electrical connections.